(1) Field of the Invention
This invention relates to the fabrication of integrated circuit devices and more particularly to a method of local oxidation with global planarization using flood exposure in the fabrication of integrated circuits.
(2) Description of the Prior Art
Local oxidation of silicon is the conventional lateral isolation scheme. The conventional local oxidation process (LOCOS) is described in VLSI Technology, International Edition, by S. M. Sze, McGraw-Hill Book Company, NY, NY, c. 1988 by McGraw-Hill Book Co., pp. 473-474. A layer of silicon nitride is deposited over a pad oxide overlying a silicon substrate. The pad oxide is a thin thermal oxide which allows better adhesion between the nitride and silicon and acts as a stress relaxation layer during field oxide formation. The nitride and oxide layers are etched to leave openings exposing portions of the silicon substrate where the local oxidation will take place. A boron channel-stop layer is ion implanted into the isolation regions. The field oxide is grown within the openings and the nitride and pad oxide layers are removed. This completes the local oxidation.
On pp. 476-477 of the aforementioned textbook, Sze describes some of the disadvantages of the growth of field oxide using the local oxidation method. The field oxide will penetrate under the masking nitride layer causing the space between transistors to grow during oxidation. This oxide growth under nitride is called "bird's beak encroachment." Other problems include stress in the oxide in the region covered by the nitride mask, white ribbon effect (a narrow region of nonoxidized silicon), thinning of the field oxide in narrow openings, and a non-recessed surface.
Many new isolation processes have been developed to overcome these drawbacks. Trench isolation schemes are the most attractive candidates. Typically, deep narrow trenches are used to isolate one device from another. Shallow trenches are used to isolate elements within a device, and wide trenches are used in areas where interconnection patterns will be deposited. Unfortunately, simple trench isolation method cannot be implemented on large area openings. A number of solutions to this problem have been proposed. U.S. Pat. No. 4,836,885 to Breiten et al and U.S. Pat. No. 4,876,216 to Tobias et al describe methods for overcoming trench isolation problems using resist etchback techniques. U.S. Pat. No. 4,656,497 to Rogers et al uses reflow of doped glass at high temperatures. U.S. Pat. No. 5,017,999 to Roisen et al, U.S. Pat. No. 5,108,946 to Zdebel et al, and U.S. Pat. No. 5,130,268 to Liou et al describe using reoxidation of solid-phase growth polysilicon. U.S. Pat. No. 4,211,582 to Horng et al and U.S. Pat. No. 4,988,639 to Aomura use two step oxidation with plurality mask techniques and U.S. Pat. No. 4,868,136 to Ravaglia and U.S. Pat. No. 5,096,848 to Kawamura describe a combination of LOCOS and trench techniques. However, in each of these processes there exist some inherent drawbacks such as productivity, repeatability, complexity, and maturity, as well as global planarization.